In the prior art, delay times are usually controlled with the aid of a simple circuit having a constant current source, a capacitor, which is connected in series with the current source and which stores the charge of a current over time with a characteristic charging curve, and a comparator, which is connected in parallel with the capacitor and which compares the voltage generated by a charge in the capacitor with a threshold value. The circuit uses the comparator to signal when a specific delay time has elapsed. To that end, the capacitor, which has a specific selected capacitance, is charged with a selected current of the constant current source, the charging duration depending on the selected capacitance and the selected current. If the voltage in the capacitor reaches a threshold voltage, this is signaled on account of a positive threshold value comparison at a comparator output. The duration until the signaling of the positive threshold value comparison corresponds to the delay time. The signaling can then be used in an integrated circuit for driving elements thereof, such as e.g. for enabling a read-in or -out operation of memory cells in a dynamic random access memory (DRAM).
The current sources in circuits for controlling a delay time usually comprise so-called “current mirrors”. A current mirror comprises, by way of example, a first transistor, through which a reference current flows, and a second transistor, whose gate is connected to the gate of the first transistor and through which a mirror current flows, which has a specific relationship with the reference current depending on the transistor parameters. This mirror current is then used for charging the abovementioned capacitor.
One disadvantage of such circuits for controlling delay times is that variations and inaccuracies in the transistor parameters of the current mirrors and the capacitor parameters lead to inaccuracies and variations during the generation of the delay times. Such variations are caused for example by temperature and production variations, but also, in particular, by variations in the capacitor parameters over a chip.
A further disadvantage of circuits for controlling delay times is that capacitors having very high capacitances have to be used for controlling long delay times. This on the one hand increases the area requirement and the outlay of the circuits and on the other hand leads to inaccuracies in the determination of delay times with the aid of a threshold value due to the flat charging characteristic of capacitors having a large capacitance.